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tech 24 June 2026

Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm

Samsung's innovation in 3D stacked FETs marks a significant leap in microelectronics. Discover how this technology could reshape the semiconductor industry.

Article inspired by the original source
Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm ↗ semiconductor.samsung.com

Introduction

In a field where every nanometer matters, Samsung recently unveiled a major advancement in transistors with its new 3D stacked FETs, featuring triple nanosheet channels at a 42 nm scale. This technology could redefine performance standards and energy efficiency for future electronic devices.

What is a 3D Stacked FET?

3D stacked FETs are an evolution of traditional transistors. While conventional transistors use a planar structure, 3D FETs leverage a vertical architecture, allowing a higher density of transistors on a chip. This approach not only boosts performance but also reduces energy consumption.

Benefits of Triple Nanosheet Channels

The use of triple nanosheets in these FETs optimizes electrostatic control and enhances charge carrier mobility. Consequently, this results in improved operational performance and reduced energy losses. According to Samsung, this technology could enable processors to deliver up to 50% more performance while consuming 30% less energy.

Why is 42 nm Significant?

At first glance, a size of 42 nm might seem like a step back compared to finer etching processes like 5 nm or 3 nm. However, that’s not the case. Samsung uses this size to optimize the fabrication and reliability of new transistor architectures while maintaining competitive production costs. These dimensions also allow exploration of new applications where miniaturization constraints are less stringent but performance is crucial.

Potential Applications

3D stacked FETs could transform multiple industries, from smartphones to data centers. With their increased performance and energy efficiency, they are perfectly suited for AI and machine learning applications, where intensive computations and efficient energy management are essential.

Challenges and Outlook

Despite its promises, implementing 3D stacked FETs poses challenges. Manufacturing processes need to be adjusted to handle the increased complexity of vertical architectures. Moreover, integrating this technology on a large scale will require investments in R&D and infrastructure.

Conclusion

Samsung continues to push the boundaries of innovation with its 3D stacked FETs. As this technology emerges, it could well become the standard for future electronic devices, transforming both device performance and energy consumption. Let's discuss your project in 15 minutes.

Samsung 3D stacked FETs nanosheets transistors semiconductors
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