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tech 8 July 2026

Why False Sharing Alignment Should Be 128 Bytes on x64

False sharing alignment is a challenge for multi-threaded systems. Discover why a 128-byte alignment can reduce inefficiencies and boost performance.

Article inspired by the original source
Why false sharing alignment should be 128 bytes on x64 ↗ monoid.github.io

Introduction

In the realm of modern processor architecture, efficiency is key. Developers and engineers spend a significant amount of time optimizing system performance, and one of the critical concepts to understand is false sharing. This issue can lead to substantial performance degradation in multi-threaded systems. This article explores why a 128-byte alignment might be the ideal solution, especially on x64 architectures.

What is False Sharing?

False sharing occurs when multiple threads access atomic variables located on the same cache line. For example, imagine a queue where two atomic pointers are used: one for the head, another for the tail. If these pointers are adjacent in memory, they could reside on the same cache line, leading to unnecessary contention when one is updated.

The consequence? Each update makes the cache line "dirty," requiring coordination between CPUs. This can turn memory management into an inefficient game of ping-pong.

Solutions and Recommended Alignment

The straightforward solution is to separate these atomic variables so that they reside on different cache lines. Modern languages like Rust and C++ offer alignment directives to help with this. For instance, #[repr(align(N))] in Rust or alignas(N) in C++.

But why 128 bytes instead of 64? Since the Intel Sandy Bridge architecture, the spatial prefetcher may load cache lines in pairs. This doesn’t double the effective cache line size but has side effects that justify a 128-byte alignment to minimize conflicts.

Empirical Evidence and Benchmarks

Tests have shown that by simply starting two threads, each updating an atomic variable, MESI (Modify, Exclusive, Shared, Invalid) interactions can be minimized if the variables are well-aligned. A typical benchmark might consist of a vector of atomics where each element is spaced 128 bytes apart.

For example, on Amazon Web Services, using c5d (Skylake) and c6i (Ice Lake) instances to test these alignments demonstrated performance gains. Apple Silicon M1, with its unique architecture, also offers interesting yet slightly different perspectives.

Conclusion

Ultimately, false sharing alignment is a subtle but significant optimization for multi-threaded systems. By using a 128-byte alignment, you can potentially reduce inefficiencies caused by false sharing and enhance the overall performance of your application.

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